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Si1141/42/43
encountered. An I 2 C write access with only two bytes is typically used to set up the Si1141/42/43 internal address
in preparation for an I 2 C read.
The I 2 C read access, like the I 2 C write access, begins with a start or restart condition. In an I 2 C read, the I 2 C
master then continues to clock SCK to allow the Si1141/42/43 to drive the I 2 C with the internal register contents.
The Si1141/42/43 also supports burst reads and burst writes. The burst read is useful in collecting contiguous,
sequential registers. The Si1141/42/43 register map was designed to optimize for burst reads for interrupt
handlers, and the burst writes are designed to facilitate rapid programming of commonly used fields, such as
thresholds registers.
The internal register address is a six-bit (bit 5 to bit 0) plus an Autoincrement Disable (on bit 6). The Autoincrement
Disable is turned off by default. Disabling the autoincrementing feature allows the host to poll any single internal
register repeatedly without having to keep updating the Si1141/42/43 internal address every time the register is
read.
It is recommended that the host should read PS or ALS measurements (in the I 2 C Register Map) when the Si1141/
42/43 asserts INT. Although the host can read any of the Si1141/42/43's I 2 C registers at any time, care must be
taken when reading 2-byte measurements outside the context of an interrupt handler. The host could be reading
part of the 2-byte measurement when the internal sequencer is updating that same measurement coincidentally.
When this happens, the host could be reading a hybrid 2-byte quantity whose high byte and low byte are parts of
different samples. If the host must read these 2-byte registers outside the context of an interrupt handler, the host
should “double-check” a measurement if the measurement deviates significantly from a previous reading.
I 2 C Broadcast Reset: The I 2 C Broadcast Reset should be sent prior to any I 2 C register access to the Si114x. If
any I 2 C register or parameter has already been written to the Si114x when the I 2 C Broadcast Reset is issued, the
host must send a reset command and reinitialize the Si114x completely.
SCL
SDA
SLA6
SLA5-0
R/W
D7
D6-0
START
Slave Address + R/W
ACK
Data Byte
NACK
STOP
Figure 8.
I 2 C
Bit Timing Diagram
Figure 9. Host Interface Single Write
Figure 10. Host Interface Single Read
Figure 11. Host Interface Burst Write
Figure 12. Host Interface Burst Read
Rev. 1.3
15
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